Stanford Root

Schedule

Stanford Root

Schedule

EE 109

Digital Systems Design Lab

UNITS:4
GRADING:Letter or Credit/No Credit
LEVEL:Undergrad
GER:WIM

The design of integrated digital systems encompassing both customized software and hardware. Software/hardware design tradeoffs. Algorithm design for pipelining and parallelism. System latency and throughput tradeoffs. FPGA optimization techniques. Integration with external systems and smart devices. Firmware configuration and embedded system considerations. Enrollment limited to EE 25; preference to graduating seniors.

Syllabus for selected term:
View Spring 2027 Syllabus

Sections

1 Term
Lecture 1Open
ID: 1966
0 / 35 enrolled
DAYS:Monday, Wednesday
TIME:10:30 AM – 11:20 AM
LOCATION:TBD
INSTRUCTOR:
Olukotun, Oyekunle
4units
Lab Section 1Open
ID: 1967
0 / 30 enrolled
DAYS:TBD
TIME:TBD
LOCATION:TBD
4units

EE 109: Digital Systems Design Lab

4 units · Letter or Credit/No Credit · GER: WIM

The design of integrated digital systems encompassing both customized software and hardware. Software/hardware design tradeoffs. Algorithm design for pipelining and parallelism. System latency and throughput tradeoffs. FPGA optimization techniques. Integration with external systems and smart devices. Firmware configuration and embedded system considerations. Enrollment limited to 25; preference to graduating seniors.

Offered in Spring 2027 at Stanford University.

Spring 2027 sections

  • Lab Section — TBA TBA (Undergrad)
  • Lecture — Monday Wednesday 10:30 AM – 11:20 AM — Olukotun, Oyekunle (Undergrad)

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