This hands-on course guides students through the complete workflow of designing a real analog integrated circuit in a modern CMOS process from transistor-level schematics to post-layout extracted verification. Students will learn to use industry-standard design tools to capture schematics, run pre- and post-layout simulations, implement physical layout, perform DRC/LVS, and evaluate performance across process, voltage, and temperature corners. Working in small teams, students will architect, design, and verify an original analog chip from the ground up, culminating in a final tapeout and submission for fabrication at the end of the course.
3-5 units · Letter or Credit/No Credit
This hands-on course guides students through the complete workflow of designing a real analog integrated circuit in a modern CMOS process from transistor-level schematics to post-layout extracted verification. Students will learn to use industry-standard design tools to capture schematics, run pre- and post-layout simulations, implement physical layout, perform DRC/LVS, and evaluate performance across process, voltage, and temperature corners. Working in small teams, students will architect, design, and verify an original analog chip from the ground up, culminating in a final tapeout and submission for fabrication at the end of the course.
Offered in Spring 2027 at Stanford University.