Provides a quick introduction to MOS transistors and IC fabrication and then creates abstractions to allow you to create and reason about complex digital systems. It uses a switch resistor model of a transistor, uses it to model gates, and then shows how gates and physical layout can be synthesized from Verilog or SystemVerilog descriptions. Most of the class will be spent on providing techniques to create designs that can be validated, are low power, provide good performance, and can be completed in finite time.
3 units · Letter or Credit/No Credit
Provides a quick introduction to MOS transistors and IC fabrication and then creates abstractions to allow you to create and reason about complex digital systems. It uses a switch resistor model of a transistor, uses it to model gates, and then shows how gates and physical layout can be synthesized from Verilog or SystemVerilog descriptions. Most of the class will be spent on providing techniques to create designs that can be validated, are low power, provide good performance, and can be completed in finite time.
Offered in Autumn 2026 at Stanford University.